Semiconductor device having a capacitor and method for the manufacture thereof

ABSTRACT

A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (Al x O y ) layer.

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor device and, moreparticularly, to a semiconductor device having a capacitor structure foruse in a memory cell and a method for the manufacture thereof.

DESCRIPTION OF THE PRIOR ART

[0002] As is well known, a dynamic random access memory (DRAM) with amemory cell comprised of a transistor and a capacitor has a higherdegree of integration mainly by down-sizing through micronization.However, there is still a demand for downsizing the area of the memorycell.

[0003] To meet this demand, several methods have been proposed, such asa trench type or a stack type capacitor, which is arrangedthree-dimensionally in a memory device to reduce the cell area availableto the capacitor. However, the process of manufacturing athree-dimensionally arranged capacitor is a long and tedious one andconsequently incurs high manufacturing costs. Therefore, there is astrong demand for a new memory device that can reduce the cell areawhile securing a requisite volume of information without requiringcomplex manufacturing steps.

[0004] Thus, to meet the demand, DRAM devices employ a high dielectricmaterial as a capacitor thin film, such as barium strontium titanate(BST) and tantalum oxide (Ta₂O₅). While DRAM is small, inexpensive,fast, and expends little power, DRAM memory has problems in that it isvolatile and has to be refreshed many times each second.

[0005] In an attempt to solve the above problems of conventional DRAM,there has been proposed a ferroelectric random access memory (FeRAM)where a capacitor thin film with ferroelectric properties such asstrontium bismuth tantalate (SBT) and lead zirconate titanate (PZT) isused for a capacitor in place of a conventional silicon oxide film or asilicon nitride film. FeRAM has a non-volatile property due to remnantpolarization of a ferroelectric material and it can operate at lowervoltages.

[0006] In manufacturing a memory device such as DRAM and FeRAM, there isa step of forming a passivation layer on top of a metal interconnectionlayer, for protecting the semiconductor device from exposure todetrimental environmental factors such as moisture, particles or thelike. The passivation layer is formed by using a method such as plasmaenhanced chemical vapor deposition (PECVD) in hydrogen rich ambient.However, during the formation of the passivation layer, the hydrogen gasgenerated by the PECVD process degrades the capacitor of the memorycell. That is, the hydrogen gas and ions penetrate to a top electrodeand a side of the capacitor, reaching to the capacitor thin film andreacting with oxygen atoms constituting the ferroelectric material ofthe capacitor thin film.

[0007] In addition, while an inter-metal dielectric, such as one made ofa spin on glass base, is formed after a formation of a metalinterconnection, hydrogen atoms may diffuse into the capacitor, therebydegrading the capacitor structure.

[0008] These problems, therefore, tend to make it difficult to obtainthe desired reproducibility, reliability and yield in fabricating thememory cell.

SUMMARY OF THE INVENTION

[0009] It is, therefore, an object of the present invention to provide asemiconductor device incorporating therein a hydrogen barrier layerprovided with an aluminum oxide (Al_(x)O_(y)) layer to protect acapacitor from hydrogen damage during the formation of an inter-metaldielectric (IMD) layer and a passivation layer.

[0010] It is another object of the present invention to provide a methodfor manufacturing a semiconductor device incorporating therein ahydrogen barrier layer provided with an aluminum oxide (Al_(x)O_(y))layer to protect a capacitor from hydrogen damage during the formationof the IMD layer and the passivation layer.

[0011] In accordance with one aspect of the present invention, there isprovided a semiconductor device for use in a memory cell, including anactive matrix provided with a transistor and a first insulating layerformed around the transistor; a capacitor structure, formed on top ofthe first insulating layer, composed of a bottom electrode, a capacitorthin film placed on top of the bottom electrode and a top electrodeformed on top of the capacitor thin film; a second insulating layerformed on top of the transistor and the capacitor structure; a metalinterconnection formed on top of the second insulating layer and theactive matrix to electrically connect the transistor to the capacitorstructure; and a hydrogen barrier layer formed on top of the metalinterconnection, wherein the hydrogen barrier layer is made of analuminum oxide (Al_(x)O_(y)) layer.

[0012] In accordance with another aspect of the present invention, thereis provided a method for manufacturing a semiconductor device includingthe steps of a) preparing an active matrix provided with a transistorand a first insulating layer formed around the transistor; b) forming acapacitor structure on top of the first insulating layer, wherein thecapacitor structure includes a capacitor thin film made of aferroelectric material; c) forming a second insulating layer on top ofthe capacitor structure and transistor; d) forming a metalinterconnection layer and patterning the metal interconnection into apredetermined configuration to electrically connect the transistor tothe capacitor structure; and e) forming a hydrogen barrier layerprovided with an aluminum oxide (Al_(x)O_(y)) on top of the metalinterconnection.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects and features of the present inventionwill become apparent from the following description of the preferredembodiments given in conjunction with the accompanying drawings, inwhich:

[0014]FIG. 1 is a cross sectional view setting forth a semiconductordevice in accordance with a preferred embodiment of the presentinvention; and

[0015]FIGS. 2A to 2G are cross sectional views setting forth a methodfor the manufacture of the semiconductor memory device in accordancewith the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] There are provided in FIG. 1 and FIGS. 2A to 2G cross sectionalviews of a semiconductor device 100 for use in a memory cell and crosssectional views setting forth a method for the manufacture thereof inaccordance with a preferred embodiment of the present invention. Itshould be noted that like parts appearing in FIG. 1 and FIGS. 2A to 2Gare represented by like reference numerals.

[0017] In FIG. 1, there is provided a cross sectional view of theinventive semiconductor device 100 including an active matrix 110, acapacitor structure 150, a second insulating layer 126, a bit line 134,a metal interconnection 136, a hydrogen barrier layer 138 provided withan aluminum oxide (Al_(x)O_(y)) layer, and an inter-metal dielectric(IMD) layer 140 formed on the bit line 134 and the hydrogen barrierlayer 138. In the embodiment of the present invention, the IMD layer 140is formed in a shape of a triple layer provided with a SiON layer havinga thickness of about 100 nm, a SOG layer having a thickness of about 400nm and a SRO (silicon rich oxide) layer having a thickness of about 400nm. The IMD layer 140 is accomplished by using a method such as the CVDor the PVD. The hydrogen barrier layer 138 is formed to a thicknessranging from 2 nm to 100 nm by using a method such as an atomic layerdeposition (ALD) and a physical vapor deposition (PVD). Here, thehydrogen barrier layer 138 plays a role in preventing the capacitor ofthe semiconductor device 100 from being degraded by hydrogen penetrationthereinto, because the diffusion velocities of hydrogen atoms markedlydecrease in the Al_(x)O_(y) layer.

[0018] In addition, a passivation layer 144 is formed on top of the bitline 134, the IMD layer 140 and the second insulating layer 126 by usinga plasma enhanced chemical vapor deposition (PECVD) technique, which iscarried out at a high temperature ranging from approximately 320° C. toapproximately 400° C., in hydrogen rich ambient. In the presentinvention, the passivation layer 144 is a double layer provided with anundoped silicate glass (USG) layer and a Si₃N₄ layer.

[0019] In the semiconductor device 100, the bit line 134 is electricallyconnected to a diffusion region 106A and a top electrode of thecapacitor structure 150 is electrically connected to another diffusionregion 106 through the metal interconnection 136, such that the bit line134 and the metal interconnection 136 are electrically disconnected fromeach other. A bottom electrode of the capacitor structure 150 may beconnected to a plate line (not shown) to apply a common constantpotential thereto. Further, between the bottom and the top electrodes,there is a capacitor thin film made of a ferroelectric material such asSBT (SrBiTaO_(x)), PZT (PbZrTiO_(x)) or the like. Here, a referencenumeral 125 denotes a TiN adhesion layer formed on the top electrode,for enhancing the connection between the top electrode and the metalinterconnection 136.

[0020]FIGS. 2A to 2G are schematic cross sectional views setting forththe method for manufacture of a semiconductor memory device 100 inaccordance with the preferred embodiment of the present invention.

[0021] The process for manufacturing the semiconductor device 100 beginswith the preparation of an active matrix 110 including a semiconductorsubstrate 102, an isolation region 104, diffusion regions 106, 106A, agate oxide 112, a gate line 113, a spacer 114 and a first insulatinglayer 116, as shown in FIG. 2A. One of the diffusion regions serves as asource and the other diffusion region serves as a drain. The firstinsulating layer 116 is made of a material such asboron-phosphor-silicate glass (BPSG) or medium temperature oxide (MTO)or the like.

[0022] Thereafter, a buffer layer 118, e.g., made of Ti or TiO_(x), isformed on top of the first insulating layer 116 with a thickness rangingfrom 50 nm to 250 nm. A first metal layer 120, a dielectric layer 122and a second metal layer 124 with a thickness in the range of 20 nm to200 nm are formed on top of the buffer layer 118, subsequently. In thepreferred embodiment, the dielectric layer 122 is made of aferroelectric material such as strontium bismuth tantalate (SBT), leadzirconate titanate (PZT) or the like and is formed by using a methodsuch as a spin coating or a chemical vapor deposition (CVD).

[0023] In an ensuing step as shown in FIG. 2B, the second metal layer124 is patterned into a first predetermined configuration to obtain atop electrode 124A and a capacitor thin film 122A. The dielectric layer122, the first metal layer 120 and the buffer layer 118 are thenpatterned into a second predetermined configuration to obtain acapacitor thin film 122A and a bottom electrode structure, therebyforming a capacitor structure 150 having a buffer 118A, a bottomelectrode 120A, a capacitor thin film 122A and a top electrode 124A. Itis preferable that the bottom electrode 120A have a size different fromthat of the top electrode 124A in order to form a plate line (not shown)during the following processes.

[0024] In a next step as shown in FIG. 2C, a second insulating layer126, made of a material such as BPSG, MTO or double layer consisting ofBPSG and tetra-ethyl-ortho-silicate (TEOS)-based oxide, is formed on topof the capacitor structure 150 and the first insulating layer 116 byusing a method such as CVD. The second insulating layer 126 is flattenedby means of a BPSG flow process or chemical mechanical polishing (CMP),as shown in FIG. 2C. In order to densify the second insulating layer126, an annealing process is carried out at a temperature ranging fromapproximately 500° C. to approximately 900° C. for at least 10 minutesin N₂/O₂ ambient.

[0025] In an ensuing step, as shown in FIG. 2D, a first opening 128 anda second opening 130 are formed at positions over the diffusion regions106A, 106 through the second and the first insulating layers, 126, 116,respectively, by using a method such as a photolithography and a plasmaetching, e.g., reactive ion etching (RIE). A third opening 132 is formedat a position over the capacitor structure 150 through the secondinsulating layer 126 by using a method such as photolithography andplasma etching. Finally, a TiN layer 125 is formed on top electrode 124Aof the capacitor structure 150 through the third opening 132, forenhancing the connection between the top electrode 124A and a metalinterconnection 136. But, the TiN layer 125 may be omitted.

[0026] Thereafter, the metal interconnection layer, e.g., made ofTi/TiN/Al, is formed over the entire surface including the interiors ofthe openings 128, 130, 132 and is patterned into a third configurationto form a bit line 134 and a metal interconnection 136, as shown in FIG.2E.

[0027] In a next step, as shown in FIG. 2F, a hydrogen barrier layer 138made of an aluminum oxide layer (Al_(x)O_(y)) is formed on top of themetal interconnection 136 by using a method such as an atomic layerdeposition (ALD) and a physical vapor deposition (PVD). Thereafter, aninter-metal dielectric (IMD) layer 140 made of a spin on glass (SOG)layer is formed on top of the bit line 134 and the hydrogen barrierlayer 138. In the embodiment of the present invention, the IMD layer 140is formed in the shape of a triple layer provided with a SiON layer of100 nm, a SOG layer of 400 nm and a SRO (silicon rich oxide) layer of400 nm. The IMD layer is formed by using a method such as the CVD or thePVD. It is noted that the hydrogen barrier layer 138 should cover thecapacitor structure 150 sufficiently to protect the capacitor structure150 effectively from hydrogen damage.

[0028] Finally, as shown in FIG. 2G, a passivation layer 144, e.g., adouble layer provided with an undoped silicate glass (USG) and Si₃N₄, isformed on the entire surface by using a method such as a plasma enhancedchemical vapor deposition (PECVD) method to protect the semiconductordevice 100 from exposure to detrimental environmental factors such asmoisture, particles or the like. The formation of the passivation layeris carried out at a high temperature ranging from approximately 320° C.to 400° C., in hydrogen rich ambient.

[0029] By structuring the semiconductor device 100 of the presentinvention as aforementioned, it is possible to prevent the capacitorstructure 150 from being damaged by hydrogen penetration thereinto. Thatis, by means of the formation of the hydrogen barrier layer 138 providedwith the Al_(x)O_(y) layer, hydrogen damage is effectively avoidedbecause diffusion velocities of hydrogen atoms are remarkably decreasedin the Al_(x)O_(y) layer.

[0030] While the present invention has been described with respect tothe particular embodiments, it will be apparent to those skilled in theart that various changes and modifications may be made without departingfrom the scope of the invention as defined in the following claims.

What is claimed is:
 1. A semiconductor device for use in a memory cell,comprising: an active matrix provided with a transistor and a firstinsulating layer formed around the transistor; a capacitor structure,formed on top of the first insulating layer, composed of a bottomelectrode, a capacitor thin film placed on top of the bottom electrodeand a top electrode formed on top of the capacitor thin film; a secondinsulating layer formed on top of the transistor and the capacitorstructure; a metal interconnection formed on top of the secondinsulating layer and the active matrix to electrically connect thetransistor to the capacitor structure; and a hydrogen barrier layerformed on top of the metal interconnection, wherein the hydrogen barrierlayer is made of an aluminum oxide (Al_(x)O_(y)) layer.
 2. Thesemiconductor device as recited in claim 1, wherein the hydrogen barrierlayer is formed to a thickness ranging from approximately 2 nm to 100 nmby using a method selected from the group consisting of an atomic layerdeposition (ALD) and a physical vapor deposition (PVD).
 3. Thesemiconductor device as recited in claim 1, wherein the metalinterconnection includes a material selected from the group consistingof titanium (Ti), titanium nitride (TiN), aluminum (Al) and combinationsthereof.
 4. The semiconductor device of claim 1, further comprising: aTiN adhesion layer for connecting the metal interconnection and the topelectrode, formed on top of the top electrode; an inter-metal dielectric(IMD) layer formed on top of the hydrogen barrier layer; and apassivation layer formed on top of the metal interconnection by using aplasma enhanced CVD in a hydrogen rich ambient.
 5. The semiconductor asrecited in claim 4, wherein the IMD layer is a triple layer providedwith a SiON layer of 100 nm in thickness, a SOG (spin on glass) layer of400 nm in thickness, and a SRO (silicon rich oxide) layer of 400 nm inthickness.
 6. The semiconductor device as recited in claim 4, whereinthe passivation layer is a double layer provided with an undopedsilicate glass (USG) layer and a Si₃N₄ layer.
 7. The semiconductordevice as recited in claim 1, wherein the capacitor thin film includes amaterial selected from the group consisting of SBT (SrBiTaO_(x)) and PZT(PbZrTiO_(x)).
 8. A method for manufacturing a semiconductor device,comprising steps of: a) preparing an active matrix provided with atransistor and a first insulating layer formed around the transistor; b)forming a capacitor structure on top of the first insulating layer,wherein the capacitor structure includes a capacitor thin film made of aferroelectric material; c) forming a second insulating layer on top ofthe capacitor structure and the transistor; d) forming a metalinterconnection layer and patterning the metal interconnection layerinto a predetermined configuration to electrically connect thetransistor to the capacitor structure; and e) forming a hydrogen barrierlayer provided with an aluminum oxide (Al_(x)O_(y)) layer on top of themetal interconnection.
 9. The method as recited in claim 8, wherein thehydrogen barrier layer is formed to a thickness ranging fromapproximately 2 nm to approximately 100 nm by using a method selectedfrom the group consisting of an atomic layer deposition (ALD) and aphysical vapor deposition (PVD).
 10. The method as recited in claim 8,wherein the metal interconnection includes a material selected from thegroup consisting of titanium (Ti), titanium nitride (TiN), aluminum (Al)and combinations thereof.
 11. The method as recited in claim 8, furthercomprising steps of: f) forming a TiN adhesion layer on top of the topelectrode for connecting the metal interconnection and a top electrode;g) forming an inter-metal dielectric (IMD) layer on top of the hydrogenbarrier layer; and h) forming a passivation layer on top of the metalinterconnection by using a plasma enhanced CVD in a hydrogen richambient.
 12. The method as recited in claim 11, wherein the IMD layer isa triple layer provided with a SiON layer of 100 nm in thickness, a SOGlayer of 400 nm thickness, and a SRO (silicon rich oxide) layer of 400nm in thickness.
 13. The method as recited in claim 11, wherein thepassivation layer is a double layer provided with an undoped silicateglass (USG) layer and a Si₃N₄ layer.
 14. The method as recited in claim11, wherein the step h) is carried out at a temperature ranging fromapproximately 320° C. to approximately 400° C.
 15. The method as recitedin claim 8, wherein the capacitor thin film includes a material selectedfrom the group consisting of SBT (SrBiTaO_(x)) and PZT (PbZrTiO_(x)).16. The method as recited in claim 8, wherein the second insulatinglayer is a double layer provided with a boron-phosphor-silicate-glass(BPSG) layer and a tetra-ethyl-ortho-silicate (TEOS)-based oxide layer.17. The method as recited in claim 8, after the step c), furthercomprising the step of annealing the second insulating layer fordensification at a temperature ranging from approximately 500° C. toapproximately 900° C. for at least 10 minutes in nitrogen and oxygenambient.